The invention is directed to a storage arrangement employing two complementary field-effect transistors which are connected in series, with the source area of one transistor being connected to the gate area of the second transistor and the gate area of the first transistor being connected to the drain area of the second transistor, while the drain area of the first transistor is connected to the source area of the second transistor.
In the development of semiconductor stores, one of the principal objectives is the production of a storage structure with a high packing density. In this connection particular interest is directed to storage elements utilizing static technology, in which the information does not require a regeneration (read regeneratively) in regular time intervals, whereby the operation of an installation is considerably simpler than that involving storage elements employing dynamic technology. German "Offlegungschrift" No. 2,348,984 there describes a static storage circuit having two complementary FET-transistors, which is suitable for the manufacture of storage elements which are small in area, with the arrangement being supplemented by peripheral circuit elements, for example a selection element and a load element. "Electronics International" Apr. 18, 1974, page 5E and "IEEE Transaction on Electron Devices," 1974, page 448, illustrate an arrangement, characterized as a "diode" consisting of two FET-transistors connected in series, whereby the gate area of the first transistor is connected to the drain area of the second transistor and the drain area of the first transistor is connected to the gate area of the second transistor. The circuit diagram of such a diode thus corresponds to the arrangement of two FET-transistors disclosed in the German "Offlegungschrift" No. 2,348,984. In "IEEE transactions" 1974, page 448, an embodiment is disclosed which is suitable for an integrated type of assembly and consists of an n-channel FET-transistor with a "back-gate" (a substrate gate), and a diffused p-channel junction field-effect transistor. The element is so constructed that the gate area of the p-channel junction transistor, together with the drain area of the first n-channel FET-transistor form a continuous doped area with the drain area of the second p-channel junction transistor and the "back-gate" of the n-channel transistor likewise involving a continuous diffused area. The element is so constructed that a p-doped area is produced in an n-substrate and two highly p-doped zones, two highly n-doped areas and a channel area which is merely n-doped are produced in the p-doped area.
The advantage of such an arrangement is that a degree of space is saved by combining the gate and drain areas. On the other hand, it has the disadvantage in that peripheral circuit elements, which are additionally necessary for the production of a storage structure, and which for example are embodied in MOS technology, cannot be manufactured in common with the method steps necessary for the manufacture of the two FET-transistors. Thus, the assembly as disclosed in the above publication requires additional method steps.